The present invention relates to an insulated gate field effect transistor, such as a power MOSFET or an insulated gate bipolar transistor (hereinunder referred to as "IGBT") and, more particularly, to an insulated gate field effect transistor and method of manufacturing the same, having a semiconductor structure in which drain, gate and source regions are vertically disposed. A conventional n-channel power MOSFET has a structure such as that shown in FIG. 3. The n-channel power MOSFET in FIG. 3 contains a high-concentration n-type drain layer 1, an n-type base layer (drain and drift regions) 2 formed thereon, a polysilicon gate 4 formed on the n-type base layer with a gate oxide film 3 therebetween, a p-type base region (channel diffusion region) 5 formed by thermal diffusion with the polysilicon gate 4 used as a mask, a high-concentration n-type source region 6, a source electrode 7 which is in conductive contact with the source region 6, an interlayer insulating film 8 for insulating the source electrode 7 from the polysilicon gate 4, and a drain electrode 9 which is formed on the back surface of the substrate. In this MOSFET, electron current flows in the transverse direction from the source region 6 to the n-type base layer through a channel inversion layer formed on the surface of the p-type base 5 right under the polysilicon gate 4, and thereafter flows in a downward vertical direction toward the drain electrode.
An IGBT has the same structure as the power MOSFET shown in FIG. 3 with a high concentration p-type minority carrier (hole) injection layer located between the drain layer 1 and the drain electrode 9. The structure of the MOS portion is the same as that of the power MOSFET.
The on-resistance R of the vertical MOSFET is represented by the following formula: EQU R=R.sub.ch +R.sub.ACC +R.sub.j +R.sub.b (1)
wherein R.sub.ch represents the channel resistance of the channel inversion layer of the MOS portion R.sub.ACC the resistance of the accumulation layer generated right under the polysilicon gate 4 except in the p-type base region 5, R.sub.J the resistance produced when electrons pass between cells, and R.sub.b the resistance of the n-type base layer 2. The resistance R.sub.b of the n-type base layer 2 is chiefly determined by the thickness, and since the thickness is substantially determined by the break down voltage planned, it is impossible to lower the resistance of the n-type base layer 2 while maintaining the breakdown voltage. Since the channel resistance R.sub.ch is dominant over the on-resistance R, in order to reduce the on R, it is necessary to reduce R.sub.ch. To reduce R.sub.ch, it is necessary to make the patterning finer so as to decrease the channel region.
The method of manufacturing the vertical power MOSFET just described will now be explained with reference to FIGS. 4(A) to 4(I). The surface of the n-type base layer 2 is first oxidized so as to form the gate oxide film 3, as shown in FIG. 4(A), and a polysilicon layer 4' is laminated on the gate oxide film 3 by CVD or the like, as shown in FIG. 4(B). After the polysilicon gate 4 is formed by patterning and etching, as shown in FIG. 4(C), impurities 10 which are to constitute the p-type base region are introduced by ion implantation or the like, as shown in FIG. 4(D), and the p-type base region 5 shown in FIG. 4(E), is formed by thermal diffusion of the impurities 10. A photoresist 11 for selecting and introducing impurities 11 is deposited at the central portion of the opening and impurities 12 are introduced by ion implantation, as shown in FIG. 4(F). The photoresist 11 is then removed and an insulating film 13 is laminated on the exposed surface, as shown in FIG. 4(G). The opening portion 8a extending over two adjacent source regions 6 is then patterned and aluminum or the like is deposited by sputtering or the like to form the source electrode 7 shown in FIG. 4(I).
An insulated gate field effect transistor having the above-described MOS structure has the following problems.
Referring to FIG. 3 the distance a between two adjacent polysilicon gates 4 is about 10 .mu.m at a minimum. Finer fabrication, which would reduce this distance a, is technically difficult because several regions are formed by a plurality of photolithography steps. Within the planar distance a, formation of the source regions 6 (FIG. 4 (F)-(G)) and patterning of the insulating film 8 must take place (FIG. 4 (H)). these steps must be carried out such that the source electrode 7, formed in 4(I), will be in contact with the source region 6. An additional requirement is that the source region 6 not contact the gate region 4. If the patterning dimension of the insulating film 8 is too small, the contact resistance increases and contact between the source region 6 and source electrode 7 may become impossible. In addition, if a is shortened too much and the difference between the a and the patterning dimension of the insulating film 8 is reduced, the source region 6 may be brought into contact with the gate region 4 by inaccurate patterning, side etching of the insulating film 8 or the like. Therefore with the prior technology, it was impossible to greatly reduce channel resistance without the great possibility of producing a defective device.
Accordingly, it is an object of the present invention to eliminate the above-described problems in the prior art and to provide an insulated gate field effect transistor, with greatly reduced channel resistance, and a method of manufacturing the same. Finer patterning is facilitated by forming a vertically oriented MOS portion in which the source region is provided near the upper portion of the gate, through the insulating film, without providing a contact portion of the source region and the source electrode between adjacent gates.